The present invention generally relates to a memory cell having a floating gate, such as the gate of a metal oxide semiconductor field effect transistor. Further, the present invention is concerned with a semiconductor memory using a plurality of such memory cells, such as an electrically erasable programmable read only memory.
Various types of semiconductor memories are known. Erasable read only memories (ROMs) are widely used. It is possible to erase data from the erasable read only memory and then write data therein. As is known, erasable read only memories are classified into erasable programmable read only memories (EPROMs) and electrically erasable programmable read only memories (EEPROMs), in view of the respective data erasing methods. Currently, it is required to reduce the electrical power consumed in EPROMs and EEPROMs.
Referring to FIG. 1, there is illustrated a conventional semiconductor memory having a floating gate. The semiconductor memory shown in FIG. 1 is composed of a data input terminal 1, a write amplifier (WA) 2, a sense amplifier (SA) 3, a capacitor C01, an N-type field effect transistor Q01 such as a MIS (metal insulator semiconductor) or MOS (metal oxide semiconductor) transistor, and a data output terminal 5. The sense amplifier 3 is made up of an amplifier 4 and a resistor R01. A high-potential side power source (line) Vcc is coupled to an input terminal of the amplifier 4, and an output terminal thereof is connected to the data output terminal 5. A connection node at which the input terminal of the amplifier 4 is connected to the resistor R01 is connected to the drain of the transistor Q01 via a sense line SL. Similarly, an output terminal of the write amplifier 2 is connected to the drain of the transistor Q01 via the sense line SL. A word line WL is coupled to the gate of the transistor Q01 via the capacitor C01. The capacitor C01 and the transistor Q01 form a memory cell of the EPROM. Data is stored, in the form of a charge, in a floating node N01 at which the capacitor C01 is connected to the gate of the transistor Q01. The source of the transistor Q01 is grounded.
Generally, the memory cell shown in FIG. 1 has two polysilicon layers formed at different layer levels. Recently, there has been proposed a single polysilicon layer structure, as shown in FIG. 2. A semiconductor substrate 6 has an impurity diffused layer (region) 7 having a conduction type opposite to that of the semiconductor substrate 6. An oxide film 8 is formed on a surface of the semiconductor substrate 6, and a polysilicon layer 9 is formed on the oxide film 8. Drain and source regions of the transistor Q01 are formed in portions of the semiconductor substrate 6 which are arranged in a direction perpendicular to the drawing sheet and located on both sides of a portion 9a of the polysilicon layer 9. The MOS type field effect transistor Q01 shown in FIG.1 is made up of the source and drain regions and the portion 9a of the polysilicon layer 9, and the capacitor C01 is made up of the impurity diffused region 7 and the remaining portion of the polysilicon layer 9. The impurity diffused layer 7 functions as a control gate and the word line WL. The polysilicon film 9 is electrically insulated from the other parts by the oxide film 8, and functions as a floating gate or node N01.
When data "1" is written into the memory cell, a high-level data signal is applied to the data input terminal 1. This data signal is applied to the drain of the transistor Q01 via the write amplifier 2. On the other hand, the word line WL is set to a high level. Thereby, electrons having a large amount of energy are generated at a pinch-off point of the drain of the transistor Q01, and pass through the oxide film 8. Then, the electrons reach the polysilicon layer 9 which functions as the floating gate 9 (corresponding to the aforementioned floating node N01), and are accumulated therein. The electrons or charges accumulated in the polysilicon layer 9 cannot be discharged because the polysilicon layer 9 is electrically isolated from the other parts. Thus, a threshold voltage V.sub.TH of the transistor Q01 is increased. On the other hand, when data "0" is written into the memory cell, no operation is carried out, and no electrons are accumulated in the polysilicon layer 9.
The data readout operation is as follows. When data "1" is stored in the memory cell shown in FIG. 1, the transistor Q01 is OFF, and no voltage drop is developed across the resistor R01. Thus, the amplifier 4 outputs a high level to the output terminal 5. On the other hand, when data "0" is stored in the memory cell, the transistor Q01 is ON, and a current passes through the transistor Q01 via the resistor R01. Thus, a voltage drop is developed across the resistor R01, and a low level substantially equal to the ground level is applied to the amplifier 4, which outputs a low level to the output terminal 5.
When erasing data "1" in the memory cell, ultra-violet rays are projected onto the polysilicon layer 9, and energy thereof is applied to the charges stored therein. Thereby, a photo current passes from the polysilicon layer 9 to the semiconductor substrate 6 through the oxide film 8, so that the polysilicon layer 9 is discharged.
However, conventional memory cells as described above have a problem in that they consume a large amount of electrical power because it is necessary to allow a direct current to pass through the sense amplifier 3 and the sense line SL when data "0" is read out from the memory cell.